Optical disk media are capable of storing a considerable amount of data in the form of small marks or holes in the surface of the disk, each representing a bit of data. The marks, burned into the surface of the disk by a laser, are arranged along spiral tracks, each divided into a number of sectors.
FIG. 1 is a diagram of an apparatus 10 for reading data prerecorded on an optical disk 12. The disk 12 is rotated by a disk servo 14 comprising a precisely controllable DC motor. A laser 16 irradiates the surface of the disk 12, and light reflected from the disk impinges on the surface of a detector 18. An optical head 20, located between the disk 12 and laser/detector 16, 18, is positioned by another servo (not shown) to read data from a desired track. Writing is carried out using similar optics, with the optical medium being preheated to enable light from laser 16 to form surface marks corresponding to data. The servos and laser/detector are controlled by a processor unit 22.
The components comprising apparatus 10 shown in FIG. 1 typically are arranged within a common housing, such as provided by SCSI (Small Computer System Interface) resident at a personal computer or other computer requiring storage of a large quantity of data.
Data read and write logic, implemented by processor unit 22 in the representative illustration of FIG. 1, has been carried out by commercially available special function integrated circuits, such as the AM95C96 optical disk controller (ODC), manufactured by Advanced Micro Devices of Sunnyvale, Calif. A system implementing the AM95C96, shown in FIG. 2, comprises ODC 24 reading data through an encoder/decoder (ODE) 28 and a phase locked loop (PLL) 30 off the optical disk and writing to the optical disk. A central processing unit (CPU) 32 controls seeking to the desired location on the disk. The ODC/ODE 24, 28 interfaces with CPU 32, working memory 34 and a disk interface 36 to process the applied data signals and transfer commands for compliance with particular specifications such as the X3B11 continuous composite servo (CCS), WORM/ERASABLE optical format developed by ANSI.
The ODC 24 is interfaced to a system bus by host interface unit 38, and is supported by buffer memory 40 and error processor 42. General operation of the system shown in FIG. 2, being known to the prior art, is not described in detail.
FIG. 3 depicts the layout of tracks on an optical disk. The tracks are arranged along a spiral path on the surface of the disk 12, with each turn of the spiral being treated as a separate track. In one example, the optical disk may be 90 mm in diameter, and may contain 10,000 tracks (numbered 0-9999 in FIG. 3); each track is divided into twenty-five (25) sectors. Each sector in turn will carry 725 bytes of unformatted data. The optical disk in this example is capable of storing 181,250,000 bytes of data, or about 100,000 pages of text. Modifications include implementing more densely packed sectors, larger diameter disks and/or double-sided storage for enhanced information storage capacity.
FIG. 4 is a field diagram of the X3B11 format, comprising a header area that is "pre-stamped", followed by a data area for receiving data for storage. The first field of the header is a sector mark (SM) having a special redundant pattern. This field identifies the start of a sector. The SM field as well as the other fields constituting the X3B11 format is summarized below in Table I.
TABLE I __________________________________________________________________________ NAME FUNCTION PATTERN __________________________________________________________________________ SM Sector Mark 80 channel bits (5 bytes) Special Redundant Patterns 5 3 3 7 3 3 3 3 50 long burn followed by 0010010010 =1111111111000000111111000000000000001111110000001111110000001111111111 0010010010 VFO1,2,3 Lock up field for PLL Continuous Pattern VFO1 = 01001001001 . . . 010010 VFO2' = 10010010010 . . . 010010 VFO2" = 00010010010 . . . 010010 VFO3 = 01001001001 . . . 010010 Note: VFO2 varies depending on previous pattern in CRC. AM Address Mark (Bit/Byte Sync) 0100 1000 0000 0100 16 Channel bits. (1 byte) ID Track No. (2 bytes) High order/Low order Sector No. (1 byte) bits 7-6=ID Number(ID 0-2) bit 5=0 Reserved bit 4-0=Sector Number CRC ID Field Check Bytes (2 bytes) CRC Polynominal seed= 1's
Postamble (one byte) Allows last CRC and DAM byte closure under RLL (2,7) modulation ODF Offset Detection Flag (one byte) Not written, no grooves GAP Gap (Splice) Unformatted area FLAG Indicate Written Block Continuous Pulse (5 byte area, decision by majority) 100100100100100100100100100 . . . ALPC Auto Laser Power Control Blank 2 bytes zone SYNC Redundant Sync for Data Triple sync pattern 0100 0010 0100 0010 0010 0010 0100 0100 1000 0010 0100 1000 DATA User Data, Control, CRC, ECC See FIGS. 1.6 and 1.7. and RESYNC bytes. BUFFER Used for RPM timing margins Not Written area RESYNC Data Field byte sync 0010 0000 0010 0100 16 Channel bits (1 byte) __________________________________________________________________________ NOTE: All bit patterns show channel code bits in RLL (2,7) modulation.
During both reading and writing operations, ODE 26 detects sector mark (SM) once within each sector. Referring to Table I, the sector mark comprises 80 bits arranged as a long burn followed by a transition pattern. Sector mark decoding is carried out by monitoring the long burn pattern of the track, and identifying a pattern characteristic of the sector mark.
Detection of the sector mark pattern is a prerequisite to the reading of data from the corresponding sector. It identifies the region of each sector from which data is to be read because the data field is displaced from the sector mark by a defined number of bytes depending upon the particular standard involved. For example, in conventional X3B11 format, shown symbolically in FIG. 4, the pre-stamped, or read only (RO), region extends 47 bytes beyond the sector mark field SM, followed by a magneto-optic region (MO) upon which data can be written once (the MO region is also termed a "WORM", or write once-read many, region). The data region of a 90 mm, 512 byte sector size by convention follows the RO region by ODF and GAP bytes. The next sector mark field follows the data field by a buffer region of 13 bytes for timing margins.
Another prerequisite of reading data from the disk is byte and bit alignment of data taken off each sector for decoding. In the X3B11 specification shown in FIG. 4, a synchronization (sync) mark of 3 bytes, signifying the start of the sector data field, follows VFO3. There are also several re-synchronization (resync) marks of one byte each at regular intervals to ensure byte alignment throughout a read operation. Following a successful header operation, the VFO3 field is searched for presence of the sync mark. Upon detection of the sync mark, a "sync found" signal is generated by the ODE and the incoming data stream is decoded one block at a time while data synchronization between the data and decoder is maintained by alignment to the resync marks.
Although the necessary functions are carried out by the prior art controller of FIG. 2, integration of the principal components, the ODC 24 and ODE 28, on separate integrated circuit "chips" is disadvantegeous in several respects.
First, because there is duplication of "intelligence" on the ODC and ODE chips and incorporation of additional interface circuitry to establish comparability between the chips, circuit and pattern layout complexity is considerable. Circuit delay is relatively high as a result of the additional length of signal paths that must be traversed between chips during handshaking and other communications.
In addition, the pair of chips necessitates microprocessor address, data and control pins to transfer data and instructions between the chips. A high pin count diminishes the versitility of the controller by prohibiting the addition of new functions, such as diagnostics, requiring user access through the pins.
Separate chip architecture also possesses other deficiencies inherent to internal operation of the controller. For example, in the prior art controller of FIG. 2, during reading of the data field, the ODC reference clock, termed RDREF, provided to the ODC 24, is derived from the phase locked loop (PLL) 30. When the loop becomes unlocked, for example as a result of a defect in the medium, the timing signal will become unstable and the ODC has a tendency to "lock up." As another example, delays in signal transfer inherent in separate chip architecture can cause X3B11 disk format incompatability or operation failure. If a command to abort a disk operation is asserted by the ODE, signal transfer protocol that must be exchanged between its internal processor and an external, main sequencer resident with the ODC, may cause the abort to be fully implemented too late.